Since 2014
A Novel Design of Low-Power 1-Bit CMOS Full-Adder Cell using XNOR and MUX
International Journal of Management and Information Technology
View Archive Info| Field | Value | |
| Title |
A Novel Design of Low-Power 1-Bit CMOS Full-Adder Cell using XNOR and MUX
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| Creator |
Lakshmaiah, Dayadi
Subramanyam, Dr. M.V. Prasad, Dr. K.Sathya |
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| Subject |
Power Delay Product; High and Low threshold voltages; parasitic capacitances; Area
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| Description |
This paper process a novel design for low power 1-bit CMOS full adder using XNOR and MUX, with reduced number of transistors using GDI cell. The circuits were simulated with supply voltage scaling from 1.2V to 0.6V &0.6V to 0.3V. To achieve the desired performance of power delay product, area, capacitance the transistors with low threshold voltage were used at critical paths and high threshold voltage at non critical paths. The results show the efficiency of the proposed technique in terms of power consumption, delay and area.
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| Publisher |
CIRWORLD
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| Date |
2012-12-30
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| Type |
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion Peer-reviewed Article |
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| Format |
application/pdf
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| Identifier |
https://cirworld.com/index.php/ijmit/article/view/702
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| Source |
INTERNATIONAL JOURNAL OF MANAGEMENT & INFORMATION TECHNOLOGY; Vol 7 No 3; 1155-1165
2278-5612 |
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| Language |
eng
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| Relation |
https://cirworld.com/index.php/ijmit/article/view/702/686
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| Rights |
Copyright (c) 2013 INTERNATIONAL JOURNAL OF MANAGEMENT & INFORMATION TECHNOLOGY
http://creativecommons.org/licenses/by/4.0 |
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